--
-- CSSE2000 8 Bit Microprocessor
-- Copyright (C) 2011 Nathan Rossi (University of Queensland)
--
-- THIS DESIGN/CODE IS PROVIDED TO YOU UNDER THE FOLLOWING LICENSE:
--
-- All material is restricted to use in the CSSE2000 Project for 2011.
-- You may not redistribute the file/code/design, without the consent of the author.
--
-- DO NOT MODIFY THIS FILE
--

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

library work;
use work.proc_package.ALL;
use work.proc_components.proc_instructionfetcher_rom;

entity proc_instructionfetcher is
	port (
		clk : in std_logic;
		en : in std_logic;
		
		addr : in PROC_PROG_ADDR_TYPE;
		value : out PROC_PROG_DATA_TYPE;
		
		-- External Memory Signals
		prog_mem_clk : out std_logic;
		prog_mem_en : out std_logic;
		prog_mem_addr : out PROC_PROG_ADDR_TYPE;
		prog_mem_data : in PROC_PROG_DATA_TYPE
	);
end proc_instructionfetcher;

architecture Behavioral of proc_instructionfetcher is
begin
	prog_mem_clk <= clk;
	prog_mem_en <= en;
	prog_mem_addr <= addr;
	value <= prog_mem_data;
end Behavioral;

